Microprocessor and Microcontroller
Microcontroller was a by-product of the microprocessor development. The same fabrication techniques and programming concepts that make possible the general purpose microprocessor also yielded the microcontroller. Microprocessors and microcontrollers stem from the same basic idea, but there are some differences between the two. A microprocessor is a general purpose digital computer central processing unit (CPU). Although popularly known as “the computer on chip”, the microprocessor is in no sense a complete digital computer. The hardware design of a microprocessor CPU is arranged so that a small or a very large system can be configured around the CPU as the application demands.
On the contrary the design of a microcontroller incorporates all of the features found in a microprocessor CPU like ALU, PC, SP and registers. It also has added other features needed to make complete computer like ROM. RAM, parallel I/O serial I/O, counters, and a clock circuit.
The microcontroller is a general purpose device, but one that is meant to read data, performs limited calculations on the data and control its environment based on these calculation. A typical microcontroller has bit manipulation instructions, easy and direct access to I/O, and quick programmed that is stored in ROM and that does not change over the lifetime of the system. Microcontroller is intended to be special purpose digital controller.
To summarize, the microprocessor is concerned with rapid movement of code and data from external addresses to the chip; the microcontroller is concerned with the rapid movement of bits within the chip.
The 8051 microcontroller generic part number actually includes a whole family of microcontrollers, which includes the 89C2051 and is available in N-Channel Metal Oxide Silicon (NMOS) and CMOS construction. The basic parts of 89C2051 and function are given below shows all the features unique to all microcontrollers:
Basic Parts of 2051
- Internal ROM and RAM
- I/O ports with programmable pins
- Timers and Counters
- Serial Data Communication
The basic parts also include the usual CPU components: program counters, ALU, working registers, and clock circuits. The 2051 architecture consists of these specific features:
- Eight-bit CPU with registers A (accumulator) and B
- Sixteen-bit program counter (PC) and data pointer (DPTR)
- Eight-bit program status word (PSW)
- Eight-bit stack pointer (SP)
- Internal ROM of 2K
- Internal RAM of 128 bytes
- Sixteen input/output pins arranged as two eight-bit ports: P1 and P3
- Two 16-bit counters TO and T1
- Full duplex serial data receiver/ transmitter :SBUF
- Control Registers :TCON, TMOD, SCON, PCON, IP, IE
- Two external and three internal interrupt sources.
- Oscillator and clock circuits.
The programming model of 2051 is a collection of 8-bit and 16-bit registers and 8 bit memory locations. These registers and memory locations can be made to operate using the software instructions that are incorporated as part of the design. The program instructions have to do with the control of the registers and digital data paths that are physically contained inside the 2051.
Each register with the exception of the program counter has an internal 1 byte assigned to it. Some registers have both bit addressing and byte addressing. Software instructions are generally able to specify a register by its address, its symbolic name, or both.
The 2051 Oscillator and Clock
The heart of the 2051 circuitry that generates the clock pulses by which all operations are synchronized. Pins XTAL1 and XTAL2 are provided for connecting a resonant network to form an oscillator. Typically a quartz crystal and capacitors are employed. The crystal frequency is the basic clock frequency of the microcontroller.
The oscillator formed by the crystal, capacitors, and on-chip inverter, generates a pulse train at the frequency of the crystal. The clock frequency f, establishes the smallest interval of time within the microcontroller, called the pulse time P. The smallest interval of time to accomplish any simple instruction, or part of a complex instruction, however is the machine cycle. The machine cycle itself is made up of 6 states. A state is the basic time interval for discrete operations of the microcontroller such as fetching an opcode byte, decoding an opcode, executing an opcode, or writing a data byte. Two oscillator pulses define each state.
Program instructions may require one, two or four machine cycles to be executed, depending on the type of instruction. Instructions are fetched and executed by the microcontroller automatically, beginning with the instruction located at ROM memory address 0000H at the time of the microcontroller is first reset.
To calculate the time any particular instruction will take to be executed, find the number of cycles C. The time to execute the instruction is then found by multiplying C by 12 and dividing the product by the crystal frequency:
T inst = (C * 12d) / Crystal frequency
Program Counter and Data Pointer
The 2051 consists of two l6-bit registers. The program counters (PC) and the data pointer (DPTR). Each is used to hold the address of a byte in the memory.
Program instruction bytes are fetched from locations in memory that are addressed by the PC. Program ROM may be on the chip at addresses 0000H to 07FFH. The PC is automatically incremented after every instruction byte is fetched and may be altered by certain instructions. The PC is the only register that does not have an internal address.
The DPTR register is made up of two 8-bit registers, named DPHDPL, which are used to furnish memory addresses for internal code access.
A and B CPU Registers
The registers A and B hold results of many instructions, particularly math and logical operations, of the central processing unit. The A (accumulator) register is the most versatile of the two CPU registers and is used for many operations, including addition, subtraction, integer multiplication and division and Boolean bit manipulations. The B register is used with the A register for multiplication and division operations and has no other function other than as a location where data can be stored.
Flags and the Program Status Word (PSW)
Flags are 1-bit registers provided to store the results of certain program instructions. Other instructions can test the conditions of the flag and make decisions based on the flag states. The flags are grouped inside the program status word (PSW) and the power control (PCON) registers.
The 2051 has four math flags that respond automatically to the outcomes of the math operations and three general purpose user flags that can be set to 1 or cleared to 0 by the programmer as desired. The math flags include Carry (C), Auxiliary Carry (AC), Overflow (OV), and Parity (P). User flags are named FO, GFO and GF1; they are general purpose flags that may be used by the programmer to record some event in the program.
The 2051 has internal RAM and ROM memory for program code bytes and for variable data that can be altered as the program runs. Unlike microcontrollers with Von Neumann architectures which can use a single memory address for either program code or data, but not for both, the 2051 has a Harvard architecture, which uses the same address, in different memories, for code and data. Internal circuitry accesses the correct memory based on the nature of the operation in progress.
The Stack and Stack Pointer
The stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve data quickly. The 8-bit stack pointer (SP) register is used to hold an internal RAM address called the top of the stack. The address held in the SP register is the location in internal RAM where the last byte of data was stored by a stack operation.
When data is to be placed in the stack, the SP increments before storing data on the stack so that the stack grows up as data is stored. As data is retrieved from the stack, the byte is read from the stack, and then the SP decrements to point to the next available byte of stored data. The SP is set to 07H when the 2051 is reset and can be changed to any internal RAM address by the programmer.
Special Function Registers
The 2051 operations that do not use the internal RAM addresses from 00h to 7FH are done by a group of specific internal registers; each called a Special Function Register (SFR), which may be addressed much like internal RAM, using the addresses from 80H to FFH. Some SFR are also bit addressable. This feature allows the programmer to change only what needs to be altered, leaving the remaining bits in that SFR unchanged.
The 2051 is organized so that data memory and program memory can be in two entirely different physic memory entities. Each has the same address ranges. A corresponding block of internal program code, contained in the internal ROM, occupies the space from 0000H to O7FFH. The program cannot be in an external ROM. Hence addresses higher than this will cause an error in the program.
Input/output Pins, Ports and Circuits
One major feature of a microcontroller is the versatility built into the I/O circuits that connect the microcontroller to the outside world. To be commercially viable the microcontroller has to incorporate as many functions as were technically and economically feasible. The main constraint was the number of pins available. For this reason, 7 of the pins may be used for one of two entirely different functions, yielding a total pin configuration of 27. The function a pin performs at any given instant depends, first on what is physically connected to it and then, on what software commands are used to “program” the pin. Both of these factors are under the complete control of the programmer and circuit designer.
Each port has a D type output latch for each pin. The SFR for each port is made up of these eight latches, which can be addressed at the SFR address for that port. The port latches should not be confused with the port pins; the data on the latches does not have to be the same as that on the pins. Different opcodes access the latch or pin states as appropriate. Port operations are determined by the manner in which the microcontroller is connected to the external circuitry.
Port 1 pin have no dual functions. Therefore the output latch is connected directly to the gate of the lower FET. Used as an input, a 1 is written to the latch, turning the lower FET off; the pin and the output to the pin buffer are pulled high by the FET load. An external circuit can overcome the high impedance pull-up and drive the pin low to input a 0 or leave the input high for a 1. If used as an output, the latches containing a 1 can drive the input of an external circuit high through the pull-up. If a zero is written to the latch, the lower FET is on, the pull-up is off, and the pin can drive the input of the external circuit low.
The port 3 is an input/output port similar in operation to port 1 the input and output operations can be programmed under the control of P3 latches or under the control of various other special function registers. Each pin of port 3 may be individually programmed to be used either as input/output or as one of the alternate functions.
Port pin alternate functions
P3.0 RxD (serial input port)
P3.1 TxD (serial output port).
P3.2 INTO (external interrupt)
P3.3 INTl (external interrupt)
P3.4 TO (Timer/counter 0 external input)
P3.5 T1 (Timer/ counter 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
Counters and Timers
Many microcontroller applications require the counting of external events, such as the frequency of the pulse train or the generation of precise internal time delay between computer actions. Both of these starts can be accomplished using software techniques. Two 16 bit up counters, named TO and T1 are provided for the general use of the programmer. Each counter may be programmed to count internal clock pulses, acting as a timer, or programmed to count external pulses as a counter.
The counters are divided into two 8 bit registers called the timer low (TLO, TL1) and high (THO, TH1) bytes. All counter actions is controlled by bits states in the timer mode control register (TMOD), the timer/counter control register (TCON), and certain program instructions.
TMOD is dedicated entirely to the two timers and can be considered to be two duplicate 4 bit registers, each of which controls the action of one of the timers. TCON has control bits and flags for the timers in the upper nibble and control bits and flags for the external interrupts in the lower nibble.
Timer counter Interrupts
The timers have been included in the chip to relieve the processor of timing and counting chores. When the program wishes to count a certain number of internal pulses or external events, a number is placed in one of the counters. The number represents the maximum countless the desired count plus one. The counter increments from the initial number to the maximum and then rolls over to zero on the final pulse and also set a timer flag. The flag condition may be tested by an instruction to tell the program that the count has been accomplished, or the flag may be used to interrupt the program.
If a counter is programmed to be a timer, it will count the internal clock frequency of the oscillator divided by 12d. The resultant timer clock must be gated to the timer. The bit TRX in the TCON register must be 0, or the external pin INTX must be a 1. The counter is configured as a timer, and then the timer pulses are gated to the counter by the bit and gate bit or the external input bits INTX.
Timer Modes of Operation
The timers may operate in any one of the four modes that are determined by the mode bits, M1 and MO in the TMOD register.
Timer Mode 0
Setting timer X mode bits to 00b in the TMOD register results in using the THX register as an 8-bit counter and the TLX as a 5-bit counter; the pulse input is divided by 32d in TL so that the TH counts the original oscillator frequency reduced by a total of 384d.
Timer Mode 1
Mode 1 is similar to Mode 0 except TLX is configured as a full 8-bit counter when the mode bits are set to 0lb in the TMOD. The timer flag would be set in .1311 seconds using a 6 MHz crystal.
Timer Mode 2
Setting the mode bits to l0b in the TMOD configures the timer to use only the TLX counter as an 8-bit counter. THX is used to hold a value that is loaded into TLX every time TLX overflows from FFH to 00H. The timer flag is also set when TLX overflows.
This mode exhibits an auto reload feature: TLX will count up from the number in THX, overflow, and be initialized again with the contents of THX.
Timer Mode 3
Timer 0 and 1 may be programmed to be in mode 0, 1 or 2 independently of a similar mode for the other timer. This is not true for mode 3. The timers do not operate independently if mode 3 is chosen for timer 0. Placing timer 1 in mode 3 causes it to stop counting; the control bit TR1 and the timer flag TF1 are then used by timer 0.
Timer 0 in mode 3 becomes two completely separate 8-bit counters. TL0 is controlled by the gate arrangement and sets the timer flag TF0 whenever it overflows from FFH to 00H. TH0 receives the timer clock (the oscillator divided by 12) under the control of TR1 only and sets the TF1 flag when it overflows.
Timer 1 may still be used in modes 0, 1 or 2, while timer 0 is in mode 3 with one important exception: No interrupts will be generated by the timer 1 while timer 0 is using the TF1 overflow flag. Switching timer 1 into mode 3 will stop it and hold whatever count is in timer 1. Timer 1 can be used for baud rate generation for the serial port, or any other mode 0, 1 or 2 function that does not depend on an interrupt (or any other use of the TF1 flag) for proper operation.
The only difference between counting and timing is the source of the clock pulses to the counters. When used as a timer, the clock pulses are sourced from the oscillator through the divide by 12d circuit. When used as a counter, pin T0 supplies pulses to counter 0, and pin T1 to counter 1. A change on the input from high to low between the samples will increment the counter. Each high and low state of the input pulse must thus be held constant for at least one machine cycle to ensure reliable counting.
Interrupts are hardware signals that force the program to call a subroutine. Software techniques use up processor time that could be devoted to other tasks; interrupts take up the processor time only when the action by the program is needed. Interrupts are often the only way in which real-time programming can be done successfully.
Interrupts may be generated by internal chip operations or provided by external circuits. Any interrupt can cause the micro to perform a hardware call to an interrupt handling subroutine that is located at a predetermined absolute address in the program memory. Five interrupts are provided in the 2051. Three of these are generated automatically by internal operations: Timer Flag 0, Timer Flag1, and the serial port interrupt (RI or TI). Two interrupts are triggered by the external circuits provided by the circuitry that is connected to pins INT0 and INT1.
All interrupt functions are under the control of the program. The programmer is able to alter the control bits in the Interrupt Enable register (IE), the Interrupt Priority register (IP), and the Timer Control register(TCON). The program can block all or any of the combination of the interrupts from acting on the program by suitably setting or clearing bits in these registers.
After the interrupt has been handled by the interrupt subroutine which is placed by the programmer at the interrupt location in program memory, the interrupted program must resume operation at the instruction where the interrupt took place. Program resumption is done by storing the interrupted PC address on the stack in RAM before changing the PC to the interrupt address in the ROM. The PC address will be restored from the stack after a RETI instruction is executed at the end of the interrupt subroutine.
Timer Flag Interrupt
When a timer/counter overflows, the corresponding Timer flag, TF0 or TF1 is set to 1. The flag is cleared to 0 when the resulting interrupt generates a program call to the appropriate timer subroutine in memory.
Pins INTO and INTl are used by external circuitry. Inputs on these pins can set the interrupt flags IEO and IE1 in the TCON register to 1 by two different method. The IEX flag may be set when the INTX pin reaches a low level, or the flags may be set when a high to low transition takes place on the 1NTX pin. Bits ITO and IT1 in TCON program the INTX pins for low-level interrupt when set to 0 and program the INTX pins for transition interrupt when set to 1. Flags IEX will be reset when a transition generated interrupt is accepted by the processor and the interrupt subroutine are accessed. The external circuit must remove the low level before an RETI is executed.
This can be considered as the ultimate interrupt as the program cannot block the action of the voltage at the RST pin. This type of interrupt is often called non-maskable interrupt. Unlike other interrupts, the PC is not stored for later program resumption.
The IE register holds the programmable bits that can enable or disable all the interrupts in the group, or if the group is enabled, each individual interrupt source can be enabled or disabled. The IP register bits may be set by the program to assign priorities among the various interrupt sources so that more important interrupts can be serviced first.
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Shivang Chugh on 2009-06-25 11:05:41 wrote,
Thanks for the description.