FPGA Based Development For Real Time Ethernet Devices - Online Article

Introduction

When it comes to implementing complex tasks in silicon, FPGA technology has progressed to the point where it challenges general purpose microprocessors and proprietary asics for many applications. This is partly due to decreasing prices coupled with increasing complexity. The outstanding flexibility and scalability of FPGAs also makes them attractive to use. Many IP (intellectual property) cores are available to enhance FPGAs with various functions, e.g. to access memory, peripherals and communication networks.

All the usual development options from the world of general purpose microprocessors ¨C such as high-performance OS, development and debugging tools and evaluation boards ¨C are now available for FPGAs. These IP-based design cores, which can include functional units up to and including complete microcontroller functions, can be transferred to future generations of FPGA devices as new silicon process technology becomes available. This presents an interesting design alternative to general purpose ¦ÌPs and asics, even for designers not presently using FPGAs.

Real-Time Ethernet in Silicon

Ethernet has been used in automation for decades, but until recently it was not possible to guarantee deterministic data exchange. This has changed during the last few years through the introduction of switches and higher transmission rates. In the near future so called Real-Time Ethernet protocols will be available for the interconnection of various field devices, like sensors, actuators, display and motion control devices. By using Ethernet and other IT protocols, seamless, bi-directional information transfer between all levels in the factory are possible.

But not all requirements can be met today by using standard Ethernet components. This is particularly true of Motion Control applications where extreme small cycle times and jitter are required.

Over the last few years companies and organisations have defined various specifications that describe how to use Ethernet and other IT protocols in field level communication systems. Also a lot of enhancements have been defined to meet the special requirements regarding jitter and cycle times. These include Profinet IO, EtherNet/IP, EtherCAT and Ethernet Powerlink to name but a few.

There is also a similar protocol diversity in the established fieldbus systems. As we learnt here, device manufacturers have to support more than one protocol in a flexible way to be present in the various markets.

This is the reason that FPGAs have such an important role in new designs. By combining the available IP cores, support for the different protocol specifications can be provided.

For example Altera's soft-core processor Nios II can be used to run the communication protocol. Ethernet-MAC and Switch cores are also available and even special additional cores exist to support the protocol-specific enhancements for various flavours of Industrial Ethernet and IEEE1588 ¨C the time synchronisation protocol which needs specific hardware support.

Display and HMI

The market demand for displays (and especially for TFT LC-displays) is expanding rapidly. First appearing in the 1970s, LCDs enjoy some standardisation in the display interface used for office appliances. However there are many different TFT panel interface types offered in the embedded computing arena. For the embedded design engineer the main challenges in the development of display systems lie in the diversity of the panel interface, the initialisation protocol and timing requirements. FPGAs can be used as a cost-efficient and quickly developed graphics and display controller design with the flexibility needed to support the selected TFT panel.

Using an FPGA in a display application can lead to a number of benefits. These include the ability to use a single platform to address the requirements of low-end, mid-range and high-end displays and selection of specific features on a project-by-project basis. FPGAs also eliminate obsolescence risk and allow additional customer requests to be incorporated late in the design cycle. Furthermore, the FPGA design offers a smooth upgrade path to new panel technologies arriving in the future.

Motion Control

Efficient and accurate control of motors is an increasingly important element of applications ranging from industrial automation to automotive systems. And with the launch of Arrow's MotionFire motor control platform, the design and implementation of motion-based applications has been made much easier for novices and motor control experts alike.

We are now going to look at three solutions to enable automation devices with Real-Time Ethernet. The first approach describes a module that can be added to any device. The other two examples combine Real-Time Ethernet with display and motion control applications. The point to be grasped is that the same FPGA can may be used for communication and either for accessing displays or for running motion control solutions.

Real-Time Ethernet

Figure 1 shows the structure of the FPGARTEM (Real-Time Ethernet-Module). This design has been developed by Softing. The module consists of a Cyclone III (EP3C40) FPGA from Altera, 32MB of DDR2- SDRAM memory, and from 8 up to 64MB of flash memory. The Ethernet interface is built by using two PHYs. This module allows the integration of an Ethernet Switch Core or the EtherCAT core to support various protocols. By integrating other cores, additional protocols such as CC-Link or EPL can be supported. Two Nios II soft core processors are integrated. The communication protocol runs on one of them. The second Nios II is available for any kind of user application. This includes simple I/O interaction with sensors and actuators, but also more sophisticated applications like web server.

Besides a unified hardware interface the software interface between the application and the various protocols is very important. A Simple Device Application Interface (SDAI) is provided to treat the various protocols in a uniform way. The SDAI supports different distribution scenarios. It can be used internally in the FPGA, if the application is running on a second Nios II. But it is also possible to attach the SDAI by using an external processor that runs the user application.

The RTEM is equipped with a flexible 40- bit connection. This connection can be used as a serial or parallel connection to peripherals (serial lines, registers, ...) depending on the FPGA design.

The Cyclone III device offers enough resource for designs using two Nios II processors and the Ethernet switch or EtherCAT IP core together with the integration of two MACs. Such a configuration can be used in various topologies. If this type of application does not need to be supported, a smaller FPGA device can be used. The EP3C25 is sufficient for simpler applications but still supports switching and EtherCAT. The EP3C16 fits very well if a device need only support one Ethernet interface.

The different vendor organisations supporting the various Real-Time Ethernet- Protocols provide well established certification procedures to make interoperability between devices of various vendors possible. Since testing can only be done together with an application the stack will be certified together with the below mentioned solutions.

Based on this design methodology a manufacturer of welding devices was able to develop a device with Profinet IO functionality within six weeks.

Display Design

Arrow's Pablo platform provides a powerful yet easy-to-use solution that enables engineers to evaluate, adapt and integrate FPGA-based graphic and display controller solutions into a target application. The Pablo reference platform is a joint development between RevisionOne Engineering and Sasco Holz.

Arrow's Pablo baseboard provides the key components, interfaces and power supply infrastructure for evaluation and prototyping. At the heart of this board is the image processing core, which combines a costeffective Altera Cyclone II FPGA (EP2C20F484C6N) with two fully independent 32-bit wide mobile DDR SDRAM memories. The mobile DDR SDRAM uses a double data rate architecture to achieve highspeed operation combined with reduced power requirements, and straightforward interface to the FPGA. The baseboard's communications options include UART, SPI and I2C connectivity as well as user-defined I/Os. LEDs, a touch digitiser, several pushbuttons and a joystick are also provided. Figure 3 (over page) shows the Pablo platform block diagram.

Each Pablo platform is delivered with design examples that have been used to verify hardware functionality and that will allow users to quickly begin developing their own application. The examples include modules for TFT and timing controllers, mobile DDR SDRAM controllers, touch controllers and miscellaneous inverter and display control functions.

To address the challenge of display interface diversity, Pablo defines a generic display interface with support for serial LVDS and parallel RGB connectivity. Various cross-adapters facilitate a seamless interface to a broad range of different TFT panels by providing the matching connectors and the required power supplies for the panels and back lighting. Depending on the adapter chosen, touch interface functionality is also available. With this concept it is easy to support many different resolutions and panel sizes from Hitachi, NEC and Sharp.

The baseboard flexibility and functionality is further extended through 'add-on' cards that comply with Altera's 'Santa Cruz' standard. Currently Arrow's range of Pablo add-on cards include options that deliver composite video input and DVI input. Each add-on card comes with its own design examples. Additional add-on cards are available through external sources offering such things as SD-CARD, 10/100/1000 Mbit Ethernet and more.

Design examples used in Pablo products feature IP cores from MaCo-Engineering and RevisionOne Engineering, in addition to reference designs and IP from Altera and Arrow. Design and consulting services for additional add-on cards, cross reference adapters and IP integration are offered by Revision One Engineering.

Based on the existing FPGA and an Ethernet add-on card, Softing has ported different Real-Time Ethernet-Protocols to the Pablo Board. Now the display solution can be integrated in RTE networks.

Example of dual view application using Sharp dual view displays

Based on the Pablo platform the consultant partner MaCo Engineering successfully implemented several customer demonstration and evaluation platforms using Sharp dual view displays. The dual directional viewing LCD panel displays different information depending on whether it is viewed from the left or from the right, for instance a simultaneous display of two images with no intermingling. Moreover, by displaying the same image on both sides, it can also function as a normal display, allowing everyone to view the same image.

Motion Control

The MotionFire platform provides all of the hardware, software and documentation needed to rapidly and cost-effectively implement motion control systems. MotionFire comprises the 'FireFighter' FPGA-based baseboard providing motor control, user I/O and network communications functionality, and plug-in 'FireDriver' motor driver power board modules. The system can support state-of-the-art motor control algorithms and communications IP and can be used to control any motor type or mix of motor types. As a result, the board is suitable for motion control applications across a variety of automotive, industrial, medical, instrumentation and consumer electronics equipment.

Motion Fire Platform

The FireFighter baseboard features an Altera Cyclone III FPGA that drives a wide variety of communication options on the board, including CAN ports, Ethernet interfaces, RS232 or RS485 connectivity and 40 protected user I/Os.

Up to six galvanically isolated ¨C by Avago's digital isolators ¨C FireDriver power modules can be connected to the baseboard. These generic 4-phase drivers provide up to 10A per channel at a DC bus voltage of 50VDC and are available with protected and filtered encoded and/or Hall effect sensor inputs. Back EMF sensing on three phases facilitates the implementation of sensorless drives, while synchronised ADC sampling is possible on all phases within the same PWM cycle. Each FireDriver has its own on-board power supply.

To support the hardware implementation, the MotionFire platform is supplied with key software and IP including a full reference design based around Altera's versatile NIOS II configurable soft processor. Advanced regulators are implemented in hardware with VHDL source provided as part of the platform, while features such as trajectory generator are implemented in software. Engineers also have access to real-time Ethernet protocol IP.

Customised IP has been developed by Swedish motor control specialist Unjo and the bespoke communication IP and RTE protocols come from Softing.

All of the designs mentioned above are available on evaluation boards and can be used as a first proof of concept.

It shows the synergy of the hard- and software integration based on Altera FPGAs and Nios II softcore CPUs. All evaluation boards come with reference designs, which can be used as a starting point for the device developer. Different IP cores can be integrated into the FPGA. This includes IP cores from Altera, third party IP cores such as those for switching or EtherCAT and optional IP cores developed in-house. The same approach can also be used for software integration. For the RTOS, eCos can be used to run the available firmware components as stacks. Special enhancements can be realised by the application software.

Synergy & Future Enhancements

The various designs can be used as self-contained solutions but they can also be combined with each other. The IP cores used for the RTE protocols and the implementation of the protocols itself are also available together with Pablo and MotionFire. This enables solutions for connecting displays to RTE as it is used by car manufacturers. The same applies for the combination of MotionFire and RTE.

Conclusion

By using FPGAs future enhancements are possible. For instance the Ethernet Switch IP core does not presently support Profinet IRT since the specification has yet to be finished. After this has been done, the core will be enhanced and can be easily updated in the FPGA designs. Since IP cores are also available for the various well established Fieldbus systems like Profibus, CAN and others, the approach may also be used to add these functions to devices.

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