Introduction To VHDL - Online Article


VHDL is a Hardware Description Language for describing digital system . VHDL a programming language, stands for VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behaviour and structure of electronic systems, but is particularly suited as a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits

VHDL is designed to satisfy a number of needs in the design process. Firstly, it allows description of the structure of a design that is how it is decompressed into sub-designs, and how those sub-designs are interconnected. Secondly, it allows the specification of the function of designs using familiar programming language forms. Thirdly, as a result, it allows a design to be simulated before manufactured, so that designers can quickly compare alternatives and test for correctness without delay and expense of hardware prototyping. VHDL contains a number of facilities for modifying the state of objects and controlling the flow of execution of modules.

The digital systems are complex ones, consisting of lots of components. As far as the automated design of such systems is concerned, methods for designing time reducing and limiting the complexity of the task are sought out and applied. A method of the kind is connected with the decomposition and hierarchy principles. The decomposition of the systems is realized in a way, which differentiates functionally independent modules.

A digital system can be described as a module with inputs and/or outputs. The electrical values on the outputs are some function of the values on the inputs.

One way of describing the function of a module is to describe how it is composed of sub-modules. Each of the sub-modules is an instance of some entity, and the ports of the instances are connected using signals. This kind of description is called a structural description.

In many cases, it is not appropriate to describe a module structurally. One such case is a module, which is at the bottom of the hierarchy of some other structural description. For example, if you are designing a system using IC packages bought from an IC shop, you do not need to describe the internal structure of an IC. In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a functional or behavioral description.

Usually, for structural and behavioral description, either Verilog or VHDL is used. In this paper a designing with VHDL is presented. Here are exposed sequentially all the phases of the very digital system's designing. The main methods are also on show here. The project descriptions' types are presented. The stress is put on the use of VHDL for synthesis of structural and behavioral models.

Methods and stages in digital systems' design

In digital systems' design, as well as design of complex systems, a couple of methods are in use:

  • Top - down designing;
  • Up - down designing.

In top - down designing the building up of the system is usually started from below in upright direction through elaborating the element blocks' schemes, assembled later to form the whole product.

An advantage of this method is the use of representation on functional block level and the lower, the structural level, is addressed only during the error check simulations within the project.

The up-down designing starts with a specification on the highest level. After that, the project is being decomposed into functional blocks and the requirements for the income and outcome time proportions are specified. The functional models are described through behavioral models or by models on register levels and are subsequently simulated.

Some of the advantages of the methods are:

  • An easier execution of the task's specifications;
  • иt allows a projects' check on system level, without tackling the structural details;
  • The project's check is done, with no regard to the technology of its realization. That allows that the choice of technology be made on a later stage of the designing project.

The most effective up-down designing method is the use of an abstract description of the scheme and the sequential details specifying of the different hierarchy levels' description.

The digital systems' design goes through the next stages:

  • Specification;
  • Functional (electrical) designing;
  • Physical designing;
  • Manufacturing;
  • Testing.

Through specification the product parameters, necessary for its proper destination, are determined.

Through the functional (electrical) designing, the electrical scheme, responsible for the functions and parameters of the product, in terms of the specification, is elaborated.

The behavioral stage serves as a description for the scheme as a system, and its entries and exits are marked out. In most of the cases, VHDL models are used.

The Functional (electrical) designing deals with main functional blocks' elaboration. Usually a detailed VHDL description of the functional block is made and being checked by a VHDL simulation.

With the increasing complexity of the projects, for the elaboration on structural level, the technique of synthesis is applied. It allows that the scheme with logical elements be synthesized from a VHDL description. Through logical description details such as charging, elements' delay, are specified and crucial methods and problems with time scattering of signals are defined.

The Physical designing stages strongly depend on technology. The common task is concerned with the deploying of the logical elements and defining (tracing) their interrelations.

Provided that for the product realization PLD, CPLD or FPGA chips are used, then the result of the physical designing represents a configuration file for designing the chosen device's resources.

The testing of the project represents a number of procedures, used by designers, to provide:

  • Adequacy between project and specification;
  • The execution of the project in terms of the chosen technology.

The designing process is usually iterative, including pre-designing of given parts, until the intended indicators are obtained.

For the tasks of testing in electrical designing (the functionality of the product and its electrical parameters), simulations are used.

The simulation on behavioral level defines how the product will run, before its actual compounding blocks are chosen. For working out of the behavioral models, the hardware description languages are used (VHDL, Verilog and others).

Through simulation, on a logical primitives level, the schemes are built up with basic logical elements "AND-NO", "OR-NO", invertors and triggers and are being simulated in order to find out irrelevances with their expected acting.

In functional testing, the delays are not concerned or they are supposed similar for all logical elements.

Error identification after the physical design

After topology's final elaboration are made the next procedures:

  • Check out of the tech norms throughout manufacturing;
  • Check out for the project's authenticity.

The tech norms for manufacturing are specific for each technological process. They include geometrical limitations for the mutual situation and the sizes of the objects in the multi-layer sketches.

The authenticity verification of the project aims to guarantee the product's proper working. It includes:

  • Finding out the interconnection of the scheme;
  • Finding out the parasite components of the topology.

Types of design descriptions

Through the designing process, three types of design description are in use:

  • Behavioral; 
  • Structural;
  • Physical.

The behavioral description tackles the system as if it were a kind of "black box" with its entrances and exits, with no regard to its structure. The aim is to ignore the redundant details and to concentrate on the specification of the necessary for the functions, which are to be done by the product. On this stage, languages for the apparatus part are used HDL (Hardware Description Languages) - VHDL, Verilog and others.

The structural description defines the way that the system is to be built up. Here, the system's structure, made of blocks and their interrelations, is tackled. The subsystems, which are to provide its functional execution, as well as their detailed description for analysis of the operational speed, charging and so on, are defined. The structural description can be presented by languages for the description of the hardware, as well as by electrical schemes.

The physical description shows exactly how, physically, this structure should be realized. For a given structural description, several physical realizations are possible. This description is connected with a concrete technological process.

The design process is connected with the transformations of the systems' descriptions and their sequential details specification. Decomposition from behavioral to structural description can be realized on a number of levels in a hierarchy. From the highest to the lowest, these levels can be outlined as it follows:

  • System level;
  • Functional level;
  • Logical level;
  • Scheme level.

On the highest system level, the system's behavior is represented by algorithms that describe its functions. In order that these functions be executed, the architecture of the system is worked out, including microprocessors, memories, main boards and other structural components.


With the increasing complexity of the projects, structural presentation on a logical elements' level, becomes a hard, even impossible. Therefore, a higher abstraction level description would allow optimal results to be reached, such as consummation, characteristics, size and price.

The hardware description language VHDL is quite suitable for purposes of that kind. It can be used for a high-level behavioral description, as well as for detailed structural description.

This language provides:

  • A standard way for documenting the project;
  • Means for creation of abstract simulation models, which can be used by each VHDL-simulator;
  • Possibility for an automatic synthesis of the electrical scheme from the project's abstract description.

The VHDL language allows the elaboration of a complete functional structural model of the specialized integral scheme, which can be simulated in order to assess its adequacy in terms of the specification's requirements. Thus, a higher quality of the project is guaranteed, because errors and problems are found out shortly after the start of the designing process.

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